The enormous speed of progress in the computer and microchip technology, respectively, is based on the successful miniaturization of the individual components of an integrated circuit. An integrated circuit is basically an electronic connection of semiconductor components and passive components for data processing, said components being produced in a thin crystal layer at the surface of a silicon substrate. The number of the integrated electronic components, such as transistors, diodes, resistors and capacitors, is very high. In order to increase the performance of the micro-chips and to lower at the same time the production cost, the packing density of the components is significantly increased in every new technology generation. The most important component of an integrated circuit is the silicon-based CMOS logic with n- or p-MOS-FET transistor (complementary metal oxide semiconductor). In particular the physical properties of silicon and silicon dioxide have allowed a substantial reduction of the transistor size in the last decades. Correspondingly, the transistor density in the microchip development could be doubled every 24 months.
Transistors are basically resistances controlled by an external gate voltage (voltage at the control electrode). Crucial performance characteristics of these components are high clock rates and a low heat dissipation in operation. Up to now, these performance characteristics could be improved by the structure reduction of the transistors. In the meantime, however, the individual component dimensions are so small that fundamental physical limits are reached and further miniaturization will not lead to an improvement. Meanwhile, besides silicon and silicon dioxide, new materials are used at this place for producing integrated circuits, the physical properties of said materials leading to an improvement of the component functionality.
In particular, the use of III/V semiconductor materials in the CMOS technology is discussed. The class of the III/V semiconductor crystals is composed of 50% each of the chemical elements of group III and group V. The binding properties of the respective chemical elements determine the electronic and optical properties of the III/V semiconductor compound. Since the composition options within the class of the III/V semiconductor materials is very large, correspondingly very different semiconductor components can be achieved. The integration of III/V semiconductor layers on Si-based integrated circuits allows on the one hand improving existing functionalities, such as the application of III/V channel layers for transistors. On the other hand, novel device concepts can be obtained, such as the integration of III/V laser diodes for optical data processing on the microchip level.
Another crucial point for the application of new materials for improving the performance of the integrated circuits is the integration process. Herein it is important, despite novel materials and/or device concepts, to keep the production costs low. Contrary to hybrid integration approaches (see for instance EP 0297483), the monolithic growth of III/V semiconductor layers on Si substrates is a very inexpensive method. Herein, the III/V semiconductor mixed crystal is directly connected with the silicon carrier substrate (see as examples only U.S. Pat. No. 5,937,274 or PCT/DE 2006/000140).
Because of the different material class of silicon and III/V semiconductors, the following aspects have to be taken into account for the monolithic connection: The atomic binding properties of silicon and of the III/V class elements are very different, consequently most III/V crystals have a lattice constant different from that of silicon. The difference of the lattice constants will in turn lead to the formation of dislocation defects during the precipitation of a III/V film on Si. Besides, an interdiffusion at the boundary between silicon and the III/V crystal and/or contamination effects during the crystal growth may lead to a doping in the respective host crystal that is difficult to control.
Another problem is caused by the different crystal base of Si and III/V crystals: If the Si surface comprises non-atomically double-layer stepped Si terraces, anti-phase defects will be formed in the III/V film. Since the 80s, the monolithic integration of III/V layers on silicon was investigated. Basically, the above challenges for the III/V precipitation on small Si substrates of up to 2 inch diameter are solved, however the formation of dislocations during the integration of III/V materials with lattice constants different from that of silicon still complicates the realization of highly efficient components with sufficient life.
Because of the different crystal base of silicon and III/V mixed crystals, anti-phase defects in the III/V layer may very quickly be formed during the monolithic precipitation. These defects in turn impair the operating properties of the components. The formation of anti-phase defects can be avoided by the specific preparation of the silicon surface.
An anti-phase-free III/V integration is possible, if by a special substrate pretreatment double-steps of two Si atomic layers each are produced. This surface preparation is however preferably possible on slightly dislocated [(001) 2° to 6° off in the <110> direction] substrates. In the document B. Kunert, I. Németh, S. Reinhard, K. Volz, W. Stolz, Thin Film Solid 17 (2008) 140, the defect-free precipitation of GaP on exactly oriented substrates was shown for the first time, however the substrate specification is still subject to an additional requirement: (001) (smaller than)<0.15° off in the <110> direction.
Since today's Si-based CMOS technology is very complex and advanced, the integration of new materials must be matched very precisely with the CMOS production process. Any larger intervention or change of the current CMOS process would significantly increase the development costs. The CMOS standard Si substrate specification with respect to the orientation is (001)+/−0.5 off in an arbitrary direction. The conversion of the CMOS technology to dislocated [(001) 2° to 6° off in the <110> direction] substrates would however by much too expensive and uneconomical due to the renewed adjustment of the process.
The above-mentioned substrate specification of (001)<0.15° off in the <110> direction would however fall into the specification of the CMOS process. However, due to this small dislocation, the specific wafer sawing process is very complicated and expensive and is still a big technological challenge. In the meantime, the Si substrate size in the actual CMOS technology is a diameter of 300 mm (some factories work with an even smaller wafer). The mass production of 300 mm Si wafers with a dislocation of <0.15° in the <110> direction would however drastically increase the production costs, and then the application of these substrates would be economically questionable. Therefore, in particular the anti-phase-free III/V integration on 300 mm Si substrates is an unsolved technological and economical problem for the CMOS process.
Another technological challenge is caused by the different thermal expansion coefficients of silicon and the compounds of the III/V semiconductor crystals. When the different dependence of the lattice constants on the temperature is not systematically taken into account in the integration process, dislocations or cracks may be formed in the III/V layer. For large substrate diameters, the Si wafer may even be affected (wafer flipping) and form relaxation defects.